By John M. Cohn, David J. Garrod, Visit Amazon's Rob A. Rutenbar Page, search results, Learn about Author Central, Rob A. Rutenbar, , L. Richard Carley
This e-book offers a close precis of study on automated format of device-level analog circuits that used to be undertaken within the past due Nineteen Eighties and early Nineteen Nineties at Carnegie Mellon college. We concentrate on the paintings at the back of the production of the instruments known as KOAN and ANAGRAM II, which shape a part of the middle of the CMU ACACIA analog CAD approach. KOAN is a tool placer for customized analog cells; ANANGRAM II a close zone router for those analog cells. we attempt to give the motivations in the back of the structure of those instruments, together with precise dialogue of the delicate know-how and circuit matters that needs to be addressed in any profitable analog or mixed-signal structure software. Our process in organizing the chapters of the e-book has been to offer our algo rithms as a sequence of responses to those very actual and intensely tough analog structure difficulties. ultimately, we current various examples of effects generated by way of our algorithms. This learn was once supported partly by means of the Semiconductor study Corpora tion, via the nationwide technology beginning, through Harris Semiconductor, and by way of the overseas company Machines company Resident examine software. ultimately, only for the list: John Cohn was once the dressmaker of the KOAN placer; David Garrod was once the dressmaker of the ANAGRAM II router (and its predeces sor, ANAGRAM I). This ebook used to be architected via all 4 authors, edited by means of John Cohn and Rob Rutenbar, and produced in complete shape by means of John Cohn.
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Additional info for Analog Device-Level Layout Automation
This model compliments the symmetry model supported by our placement algorithms. 7. Integrated Rip-up and Rerouting: To cope with the high density of highly-merged compact layouts we developed a novel method for integrating consideration of potential net rip-ups into the path search process. This rip-up capability proves to be essential to achieve layout densities close to those of human designers. 8. Crosstalk A voidance Routing: The geometry of the wires and their sur,rounding environment contributes significant inter-nodal parasitic capacitances which often affect circuit performance.
To remove the illegal overlaps, the annealer must then drive this overlap penalty to zero in the eourse of optimization. In eontrast, the slicing style speeifies object position in terms of their relative eoordinates. These are based on topologieal relations between the objects arranged around a set of slices whieh reeursively biseet the layout. The direetion and nesting of these slices is reeorded in a slicing tree. An annealer manipulating a slicing placement does not move objeets directly, rather it alters their relative positions by modifying aspects of the slicing tree itself, sueh as slice direetion.
Introduction 17 Chapter 4 describes various forms of geometry sharing, including device merging, and abutment routing, and describe the benefits of their use. We then describe the sweeping implications of incorporating geometry sharing as a placement optimization. We demonstrate the great advantage of device geometry sharing by creating layouts of our three representative circuits. We show that the layouts which incorporate both topological constraints and device geometry sharing are comparable in density and aesthetic to high-quality manual layouts.